1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a semiconductor device including a state storage circuit including redundant storage nodes.
2. Description of Related Art
In recent years, semiconductor miniaturization technology has been advanced and there has been a trend toward smaller transistor sizes. However, if a transistor of a small size is used, the amount of charge held by the drain of one transistor is reduced. For this reason, a soft error caused when radiation enters a semiconductor device has been a significant problem. A soft error refers to an error where when radiation enters the vicinity of the drain of a transistor constituting a storage node of a state storage circuit, such as a memory or a latch circuit, electrons or holes occur and data held by the storage node is lost due to the electrons.
Among examples of a circuit for enhancing resistance to such a soft error is a DICE (dual interlocked cell) circuit where circuits constituting storage nodes are made redundant to prevent loss of data held by the storage nodes. Examples of such a DICE circuit are disclosed in Japanese Patent Translation Publication No. WO/2006/016403 and T. Calin, et al., “Upset Hardened Memory Design for Submicron CMOS Technology,” IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Vol. 43, No. 6, pp. 2874-2878, Dec. 1996.
FIG. 8 shows a circuit diagram of a DICE circuit 100 described in WO/2006/016403. As shown in FIG. 8, the DICE circuit 100 basically includes four transistor pairs each including a p-type MOS transistor and an n-type MOS transistor. In FIG. 8, a pair formed by a p-type transistor 121a and an n-type transistor 122a, which is a first transistor pair, and a pair formed by a p-type transistor 121b and an n-type transistor 122b, which is a third transistor pair, are transistor pairs that make each other redundant. Likewise, a pair formed by transistors 126a and 127a, which is a second transistor pair, and a pair formed by transistors 126b and 127b, which is a fourth transistor pair, are transistor pairs that make each other redundant.
For example, a node C1 connecting the transistors 121a and 122a of the first transistor pair is connected to the gate of the p-type transistor 126a and the gate of the n-type transistor 127b. Also, the node C1 is connected to a bit line BLa via a transistor 123a. A word line WLa is connected to the gate of the transistor 123a. 
A node C2 connecting the p-type transistor 126a and the n-type transistor 127a of the second transistor pair is connected to the gate of the p-type transistor 121b and the gate of the n-type transistor 122a. Also, the node C2 is connected to a bit line BLXa via a transistor 128a. The gate of the transistor 128a is connected to a word line WLa.
Similar connections are made with respect to a node C3 of the third transistor pair and a node C4 of the fourth transistor pair. Wiring lines connecting the nodes C1 to C4 and the gates of the transistors as described above correspond to node-gate connecting means.
As seen, in the DICE circuit 100, the first and third transistor pairs make each other redundant and the second and fourth transistor pairs make each other redundant. The node connecting the p-type transistor and n-type transistor of each transistor pair is connected to the gate of the p-type transistor of the transistor pair disposed in the subsequent stage and to the gate of the n-type transistor of the transistor pair disposed in the preceding stage. By having such a configuration, even if charge exceeding a critical charge amount occurs at one node when radiation enters, the error state does not easily spread over the node in the subsequent stage nor the node in the preceding stage. Thus, the soft error tolerance is enhanced.
FIG. 9 shows an example of the layout of the DICE circuit 100. In FIG. 9, as in FIG. 8, two n-wells are disposed on both sides of a centrally disposed p-well, and two p-wells are disposed outside the n-wells. The n-type transistors 122a and 127a are disposed in the central p-well. The p-type transistors 121b and 126b are disposed in the right-hand n-well region. The p-type transistors 121a and 126a are disposed in the left-hand n-well region. The n-type transistor 122b is disposed in the most right-hand p-well. The n-type transistor 127b is disposed in the most left-hand p-well.
That is, in the DICE circuit 100, the transistors constituting the nodes C1 and C3 are disposed in the separated wells, and the transistors constituting the nodes C2 and C4 are disposed in the separated wells. Thus, the nodes C1 and C3 holding an identical logic level avoid becoming simultaneously affected by charge caused when radiation enters these nodes. The same holds true for the nodes C2 and C4 holding an identical logic level. Thus, the soft error tolerance is further enhanced.